Building the Verification Trust Layer for AI-Driven Chip Design: Why We Invested in VerifAIX
AI is getting remarkably good at writing code. It is now beginning to write the code that becomes chips.
That creates a fundamental problem: as AI increasingly generates specifications, RTL, testbenches and other parts of semiconductor design, how do you know what it generated is actually correct?
You can use another AI to check it. But in semiconductor design, where an error can make its way all the way to silicon, “probably correct” isn’t good enough.
Someone still has to verify the AI. That’s the problem VerifAIX is going after.
The Idea
Semiconductor design is entering a fundamental transition. Verification is becoming the bottleneck
Chips are becoming dramatically more complex, driven by AI accelerators, custom silicon, chiplets, advanced processors and increasingly heterogeneous system architectures. At the same time, AI is beginning to transform how those chips themselves are designed, from specifications and architecture to RTL and verification.
Chip design has always been unforgiving. A software bug can often be patched after deployment. A silicon bug discovered after tape-out can mean months of delay and an extraordinarily expensive respin.
Verification, establishing that a chip behaves according to its intended specification, is therefore one of the most critical and resource-intensive parts of semiconductor development.
And it is getting harder.
Verification teams have to reason across increasingly large specifications, RTL implementations, protocols, state spaces, test environments and billions of possible interactions. The work requires scarce, highly experienced engineering talent and can consume a significant portion of the overall chip development cycle.
AI can make parts of this process significantly faster. It can read specifications, generate assertions and testbenches, identify potential bugs and help engineers debug.
But generation is not verification.
If one probabilistic AI system generates a chip design, asking another probabilistic AI system whether that design is correct does not necessarily establish ground truth.
For verification, confidence needs to be backed by evidence.
From AI generation to AI you can trust.
This insight sits at the heart of VerifAIX.
The company is building a spec-first AI verification platform designed to become an independent verification trust layer for semiconductor development.
At the core of the platform is what the team calls the Formal Brain - a mathematically grounded understanding of a semiconductor design and its intended behaviour.
VerifAIX reasons across specifications, RTL and verification assets to identify inconsistencies and gaps. That trusted foundation can then drive verification planning, formal analysis, simulation, coverage, debug and ultimately verification closure.
For complex designs, the platform uses automated abstraction and decomposition to break large verification problems into tractable pieces while maintaining their relationship to system-level design intent. It also brings formal verification and simulation together, applying each methodology where it is most effective.
The distinction is important.
VerifAIX isn’t simply trying to generate verification code faster. It is trying to establish ground truth, traceability and reproducible evidence of correctness.
The ambition is to create the trust layer required to determine whether increasingly complex chips actually do what we intended them to do.
Why now
We believe two powerful curves are intersecting.
The first is semiconductor complexity. Processors, AI accelerators, custom silicon, chiplets, interconnects, memory systems and heterogeneous architectures are making verification problems larger and harder.
The second is AI-driven engineering productivity. AI is moving from assisting engineers to increasingly generating meaningful portions of engineering work.
That productivity increase is enormously valuable. But it creates a corresponding requirement for independent verification.
The more engineering artifacts AI generates, the greater the need for a system that can establish what is correct.
This is why we believe verification could become even more important in an AI-native semiconductor development stack.
Why VerifAIX
Three things stood out to us.
First, VerifAIX is focused on correctness alongside productivity.
AI agents and code generation will continue to improve. We believe an equally important problem is establishing a trusted understanding of design intent against which generated outputs can be verified.
Second, VerifAIX is designed to complement the existing semiconductor ecosystem.
Semiconductor companies have spent decades building sophisticated workflows around simulation, formal verification and established EDA infrastructure. VerifAIX is being built to integrate into these environments and potentially serve as a verification trust layer across them, including within customers’ emerging AI and agentic engineering systems.
This is important because verification sits directly on the critical path to tape-out. Integrating with existing workflows can allow teams to adopt new capabilities without having to fundamentally change the infrastructure they already rely on.
Third, the architecture has the potential to scale with the problem.
VerifAIX combines semiconductor-domain reasoning, formal and mathematical methods, automated abstraction and decomposition, AI, simulation and formal verification within one architecture.
The near-term focus is on complex blocks and IP. Over time, the opportunity is to extend toward subsystems and increasingly complex full systems.
A team built for a difficult problem
Semiconductor verification requires deep and specialized domain expertise.
VerifAIX was founded by Madhulima Tewari, Kenneth Roe and Avner Landver, bringing together deep experience across AI, semiconductor design, formal and functional verification, mathematical methods, EDA and complex chip development.
Madhulima has worked across AI/NLP, enterprise software and semiconductor EDA. Ken has spent decades in formal verification, including building production verification infrastructure at Intel and
working at SiFive and Synopsys. Avner brings more than 25 years of semiconductor verification experience across Apple, Intel, Cadence and IBM Research.
Vin Dham, one of the pioneers behind Intel’s Pentium processor, joins them as Founding Advisor.
What stood out to us was not simply the cumulative experience around the table. It was the combination of disciplines, and how the team approached the problem.
Many teams ask how LLMs can generate semiconductor artifacts faster.
The VerifAIX team started with a different question: What needs to be true for an engineer to trust the result?
Building that requires people who understand both the rapidly evolving capabilities of AI and the mathematical rigor demanded by semiconductor verification. VerifAIX has assembled that unusual combination.
Early validation on real semiconductor designs.
VerifAIX has moved beyond core technology development and is now applying its platform to real semiconductor designs through customer pilots and deployments.
This is an important part of the validation process. Synthetic benchmarks are useful. But production semiconductor designs are where elegant AI demos encounter reality: incomplete specifications, complex protocols, enormous state spaces, legacy verification environments and workflows that cannot simply be replaced.
The platform is being applied to complex, control-intensive and protocol-heavy designs representative of the problems semiconductor engineering teams encounter in practice.
At this stage, what matters to us is whether the technology can solve difficult verification problems in real environments, integrate into existing tool flows, create meaningful value for engineering teams and earn the trust required for broader deployment.
The early evidence gives us reason for conviction. There is also much more to prove.
The Formal Brain needs to scale from complex blocks and IP to subsystems and eventually much larger designs. Automated abstraction and decomposition need to continue working as complexity increases. The integration between formal verification and simulation needs to deepen. And ultimately, the platform needs to earn the level of trust required to become part of customers’ verification workflows.
At the Seed stage, these are the kind of risks we like to underwrite at Endiya. Building globally, with India as a critical design hub.
Semiconductor engineering is inherently global, and VerifAIX is building accordingly, with a team spanning the US, India and Israel.
India will be an important part of that journey. The country has developed significant depth in semiconductor design and verification talent and is becoming an increasingly important design center for the global semiconductor industry.
This also aligns closely with our broader thesis at Endiya: that India’s deep technical talent can increasingly serve as the foundation for globally relevant deep-tech companies.
With this financing, VerifAIX plans to deepen its engineering and R&D organization, strengthen the Formal Brain, scale abstraction and decomposition to larger designs, deepen the integration between formal verification and simulation, and support customer deployments.
This is a technically demanding category that requires an unusual combination of talent across formal verification, mathematical reasoning, AI systems, EDA and chip architecture. We believe the ability to build that team globally, with India as an important engineering base, can be a meaningful advantage.
The opportunity ahead
The near-term opportunity is clear: enable semiconductor verification teams to do substantially more with the engineers and tools they already have.
The longer-term opportunity is much larger.
As AI moves from assisting engineers to increasingly participating directly in semiconductor design, generation becomes abundant. Trust becomes scarce.
Every AI-generated specification, RTL block, assertion or testbench creates another question downstream: does this actually do what we intended?
If VerifAIX can become the independent layer that preserves design intent, reasons across what was specified and what was built, and produces reproducible evidence that the two agree, its role can extend well beyond today’s verification workflow.
It can become part of the trust infrastructure for AI-driven semiconductor development. That is the larger opportunity we see.
AI will almost certainly help us design chips faster.
The harder question is whether we can trust the chips it helps us design.
We believe VerifAIX is building an important part of that answer.
We are excited to partner with Madhulima, Ken, Avner, Vin and the broader VerifAIX team as they build the verification trust layer for the AI-native semiconductor era.